Camera Link and Channel Link Datasheet



	CAMERA LINK AND CHANNEL LINK Camera Link is a camera interfacing specification developed by the camera and frame grabber community to simplify camera/frame grabber interfacing and qualification The Camera Link specification defines: A standard connector that will be used on both the camera and the frame grabber. A standard cable to connect the camera and the frame grabber. Image formats for transmitting data from the camera to the frame grabber. Standard camera control inputs. A standard method for transmitting serial communication data between the camera and the frame grabber. A standard chip set (Channel Link by National Semiconductor) that will be used in the camera and frame grabber for data transfer. Camera Link is based the Channel Link LVDS chip set manufactured by National Semiconductor. A Channel Link chipset consists of a transmitter, DS90CR287, and a receiver, DS90CR288A, and is used to transfer digital data. The chipsets have a 3.3V supply and operates with a clock speed of 85 MHz. The transmitter converts 28 bits of CMOS/TTL data into four LVDS data streams. The data is sampled and transmitted with every cycle of the transmit clock. The receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. Using a transmit clock with a frequency of 85 MHz, 28 bits of TTL data is transmitted at 595 Mbps per LVDS channel. With four data channels the total data throughput is 2.38 Gbit/s. In the Channel Link protocol 28 bits of data are transferred over just 4 pairs of wires and a fifth pair is used to transfer a required clock signal. The basic outline of the chip functionality is diagrammed below CAMERA LINK Camera link uses the National Semiconductor's Channel Link chips as shown above to define the interface. Using one or two transmitter or receiver Channel Link chips, the standard defines a Basic, Medium, and Full Camera Link specification. Thus allowing up to approximately 800-900 MB/sec transfers at 85 MHz. This interface hierarchy is diagrammed below. Click here for the original Camera link specification or here to go to the AIA website where the official specification is available DS90CR287 OVERVIEW The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec). Both devices are also offered in 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44% reduction in PCB footprint over the 56L TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces. FEATURES 20 to 85 MHz shift clock support 50% duty cycle on receiver output clock 2.5 / 0 ns Set & Hold Times on TxINPUTs Low power consumption ą1V common-mode range (around +1.2V) Narrow bus reduces cable size and cost Up to 2.38 Gbps throughput Up to 297.5 Mbytes/sec bandwidth 345 mV (typ) swing LVDS devices for low EMI PLL requires no external components Rising edge data strobe Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead TSSOP package Both devices are also available in 64 ball, 0.8mm fine pitch ball grid array (FBGA) package DS90CR287 OVERVIEW The DS90CR287 transmitter converts four LVDS (Low Voltage Differential Signaling) data streams into 28 bits of LVCMOS/LVTTL data. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec). Both devices are also offered in 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44% reduction in PCB footprint over the 56L TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces. FEATURES 20 to 85 MHz shift clock support 50% duty cycle on receiver output clock 2.5 / 0 ns Set & Hold Times on TxINPUTs Low power consumption ą1V common-mode range (around +1.2V) Narrow bus reduces cable size and cost Up to 2.38 Gbps throughput Up to 297.5 Mbytes/sec bandwidth 345 mV (typ) swing LVDS devices for low EMI PLL requires no external components Rising edge data strobe Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead TSSOP package Both devices are also available in 64 ball, 0.8mm fine pitch ball grid array (FBGA) package